1. Field of the Invention
The present invention relates to flash memory arrays. More particularly, the present invention relates to methods and apparatus for reducing the pre-settlement time needed before a flash cell output can be sensed on a bit line in a memory array.
2. The Prior Art
Most of the prior precharging schemes known in the prior art are designed for CAM, DRAM, SRAM and ROM memory cells. These types of memories mentioned above never use a reference bit line like non-volatile memory. The sensing scheme of the above memories amplifies the difference between of one pair of differential bit lines coupled to each selected cell.
The majority of bit line precharge methods that have been adopted in the industry involve creation of a short pulse and charge up the bit line to VCC−Vt, or to VCC. Some known schemes pre-charge the target bit line to Vcc−|Vt|, or Vcc−2|Vt|. U.S. Pat. No. 6,240,020 shows a NAND type Flash memory scheme in which the bit line is precharged to VCC−Vtn. U.S. Pat. No. 5,105,354 discloses a scheme in which an extra “plateline” is used on the source side of the EEPROM memory cell. The plateline is coupled up by a substrate capacitance during precharge. When the wordline goes high, the voltage level on the source and drain sides of the memory cells are being equalized.